Digital integrated circuit chips are composed of many millions of gates that make up various functional components on a chip such as flip-flops, multiplexers, logic circuits, etc. A given chip design may have thousands of flip-flops scattered throughout the chip.
In order to effectively and efficiently test a given chip, certain test features are typically incorporated into the chip design for testing purposes. Before a chip is actually taped out and manufactured, the chip design is first simulated in software using various simulation tools such as, for example, a Verilog Test Bench. By simulating the design of the chip, the design features of the chip may be thoroughly tested before the expense and time of actually manufacturing the chip is incurred.
Pattern verification is a critical phase in testing of chips. A scan pattern is a digital string of binary ones and zeros that may be shifted through a scan chain of flip-flops in the chip design. Every scan pattern cycle is composed of two phases. The first phase is the shift phase where new data is shifted into the scan chains of flip-flops. The second phase is the capture phase where the data is captured by the various chip components by applying a clock pulse.
Typically, the flip-flops in a digital integrated circuit design are designed such that they have normal data inputs and outputs (D and Q) and test inputs such as TI (test data input) and TE (test enable input). During simulation and testing, the flip-flops may be placed in the test mode by enabling the TE input. Data may then be clocked into the flip-flops through the TI input instead of the normal D data input. During testing, the flip-flops of the chip are chained together to form multiple scan chains. The output Q of a given flip-flop is connected to the input TI of a next flip-flop. Each scan chain may comprise, typically, 5000 to 10,000 flip-flops.
One way of checking for defects in elements of CMOS chips is to perform IDDQ testing. IDDQ is the quiescent drain-drain current of a CMOS element in a chip. During a standby or quiescent state of the chip, the logic states of the elements of the chip are stable. No activity is being performed by the chip. A CMOS circuit uses very little power and, in a standby or quiescent state, draws almost no current. Only leakage current is drawn in the standby or quiescent state. However, if the current consumption observed in the standby state is higher than expected, then a defect of some type is probably present in the chip.
IDDQ testing, therefore, measures the quiescent supply current of the device under test. A CMOS circuit should not draw a significant amount of current when in a stable situation. In the quiescent state, only leakage current will flow. A larger, unexpected amount of current that is observed flowing in the quiescent state indicates that a manufacturing or design defect is likely present in the circuit.
FIG. 1 illustrates an embedded CMOS inverter comprising a PMOS transistor and an NMOS transistor. When Vin transitions (toggles) from a logic zero to a logic one, Vout toggles from a logic one to a logic zero. When Vin transitions from a logic one to a logic zero, Vout transitions from a logic zero to a logic one. As a result, IDD current is drawn by the inverter during the transition times, flowing from VDD to VSS.
When Vin and Vout are not toggling, the current drawn by the inverter is IDDQ, the quiescent current, as shown in FIG. 1. If the inverter has no defects, IDDQ is very low compared to the IDD transition current. However, if the inverter is defective (e.g., a short across one of the transistors), then IDDQ is relatively high, indicating a defect.
During simulation of the design of an integrated circuit chip, IDDQ patterns may be generated based on the design of the chip. The IDDQ patterns are designed to toggle the logic states of as many of the elements of the chip as possible in order to subsequently test the chip for defects using the IDDQ patterns and measuring the currents.
A burn-in process or test is a method used, in general, to test how a chip ages. A burn-in process is typically used to stress chips to try to induce faults in the chips. The purpose is to test the robustness of the chips and to eliminate “infant mortalities” of the chips (i.e., weed out chips that are likely to fail relatively quickly). During the burn-in process, the chips are stressed over temperature and supply voltage for a certain period of time. It is desireable, during the burn-in process, to put the chips in a dynamic operational state (i.e., toggle as many of the logic components of the chip as possible). Once the burn-in process (or a stage of the burn-in process) is complete, the chips are functionally tested to check for defects.
During the burn-in process, the chips are mounted on burn-in boards. The burn-in boards are typically circuit boards that allow the chips to be powered up and dynamically activated or exercised. The burn-in boards typically comprise memory and/or clock circuitry to exercise the chips. The burn-in boards may interface to power supplies and other test equipment in order to apply power to the chips and to exercise the elements of the chips.
During burn-in, the chips are exercised by clocking burn-in data patterns into the chips. However, the burn-in boards typically have a limited amount of memory to store the burn-in patterns and, therefore, the burn-in patterns used are often not capable of exercising a very large percentage of the chip (i.e., providing a high percentage of toggle coverage) as desired. The burn-in patterns are typically applied to the chips continuously for tens of hours.
Most of the time, the burn-in patterns used are chosen from either functional patterns that usually target a very limited area of the chip. Scan patterns are sometimes used and may provide better toggle coverage but the choice of scan patterns can be tricky because the total number of scan patterns is usually orders of magnitude larger than what may be loaded on the memory of the burn-in boards.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.